[Umberto]

Dear Rishikesh,

the last version of the files are ok, except rca_pnml. Input a0 is an output pin. Unfortunately, you triggered a bug. We have solved it and the new version of MagCAD will be released soon. Modify the rca layout using an input pin for a0 and everything will be fine.
Update to version 2.9.0 as soon as it will be available and fell free to report any problem.

[Umberto]

Dear Rishikesh,

please be careful because the files you uploaded contains some errors. For example in file xor_pnml the output overlaps the or instance. Please correct and repeat the operation.
In case you updated the files, pleas upload the latest version here.
Thanks

[Umberto]

Dear Rishikesh,

I was wrong, there is a problem in the FA file. I get an error during VHDL generation. In fact, the connection with the output of the HA are wrong. Unfortunately, there is a bug somewhere and the tool is not managing properly the error in a file deeper in the hierarchy.
We are working on it. As a workaround, please be sure that all the components in the hierarchy are error free, and generate manually the VHDL for each of them.

This will solve your issue while we work on version 2.8.1.

[Umberto]

Dear Rishikesh,

the files you provided me have an error in the xor layout. When I tried to export the component I get an error. Is it the same for you? Which version of MagCAD are you using?

[Umberto]

Dear Rishikesh,

two files, (and_pnml and or_pNML) are missing and therefore I can’t verify your issue.
Anyway, you posted in the ToPoliNano support but you are using pNML: this technology is not yet supported inside the tool.
Are you referring to MagCAD instead?

[Umberto]

Hi Anshul,
I have seen layouts with more than 13 layers. There is not a limit to the number of layers that the tool can handle. Anyway, please report here if you find some issues increasing the number of layers.
The only problem that you may face is in the fact that the color assigned to the layer are maybe 10. Therefore there will be different layers with the same color.

Best regards,
Umberto

• This reply was modified 4 years, 9 months ago by Umberto.

[Umberto]

Hi,
please attach the qll. From the picture it seems that all the inputs are correct, so I think the problem is in one of the path that feed the circled MVs.
Regards.

[Umberto]

Hi,
you can edit your layout but you can’t edit the component that you exported. Open the layout, modify what you need and then export again the component.

Regards,
Umberto

[Umberto]

Dear Divyang,
your design has multiple issues.
The PINs are mono-directional: you can’t use that to connect directly a wire.
You can’t name two pin in the same way. This will lead to an error, not to a connection.
If you want to use a circuit multiple time in a layout, please export the component associated and then use that as a black box.
Please, read carefully the documentation and the example.
Finally, even if it is possible to put different “circuit” in the same layout you should consider to avoid this practice. Keep the layout simple and use hierarchy when possible.

Regards,
Umberto

[Umberto]

Hi,
please attach also the qll of the component that are inside your design.
Some more information about the error would be useful too.
Umberto

[Umberto]

Hi,
thank you for pointing out the issue with this error. We will improve the messages in order to simplify the process.
The error is due to the fact that the nucleation on layer 1 in your design has 2 inputs, and the number of inputs must be odd.
It is correct in the second design because the pad will connect only with a nucleation in front of it. You can have a look to the documentation for the table describing all the connection for each element.

Umberto

[Umberto]

Hi,
area and latency are not going to change if you use hierarchical approach or not. Those parameters are related to the circuit design, the number of elements, the functionality and the length of the interconnections in pNML technology. The latency in pNML and in general in NML is the time from an applied input to reach the output. Similarly happens in CMOS: if I design a circuit and then place two of them in series the area and delay will increase, no matter what approach (hierarchical/flat) is used. Indeed, if you use “flat insert” for your fulladder you will get the same values as if you insert it as a component. Obviously, your previous designs are different in area and latency since they are different circuits. I report here the definitions and log files for fulladder_box and the same layout where the component has been replaced with flat elements(see pictures).

Fulladder_box                      | Fulladder_box_flat
definitions                        | definitions
-- Entity name: full_adder_box     | -- Entity name: full_adder_box_flat                                         
-- Element list:                   | -- Element list:  
--  Tmagnet         1              | --  Tmagnet         1  
--  -------------------            | --  ---------------------- 
--  via             2              |--  via             2   
--  -------------------            |--  ----------------------  
--  fa1             1              |   
--  -------------------            |--  ----------------------  
--  corner          5              |--  corner          5 
--  -------------------            |--  ----------------------  
--  Xmagnet         1              |--  Xmagnet         1   
--  -------------------            |--  ----------------------  
--  magnet          9              |--  magnet          9   
--  -------------------            |--  ----------------------  
--  mv3             3              |--  mv3             3  
--  -------------------            |--  ----------------------  
--  inverter        20             |--  inverter        20 
--  -------------------            |--  ----------------------  
--  pad             16             | --  pad             16    
--  -------------------            |--  ----------------------  
log                                |log
Bounding box area:  8.1 um^2.      |Bounding box area:  8.1 um^2.

As you can see those circuits are identical.
Let me say that those circuits are also useless: if you designed fulladder1 there is no need to design a circuit that instantiates only a fulladder1 and some interconnections. If you want a 2bit rca you need to add two fulladder1 and connect them properly.

I hope this solves your issue.
Umberto

• This reply was modified 5 years, 2 months ago by Umberto.
• This reply was modified 5 years, 2 months ago by Umberto.

Attachments:

1. 

   full_adder_box.png
   

2. 

   full_adder_box_flat.png
   

[Umberto]

Hi Saurabh,

you can use magnets, corners and pads to connect components. Please, consider that it is not needed that you create a different full_adder for each instance: the tool generate different VHDL instances for each full_adder.

Thank you for pointing out this issue. We are updating the documentation with a tutorial for hierarchical designs.
We will update the file ASAP.

[Umberto]

Hi Saurabh,
once you designed a circuit you can export it as a component. A component can be used as a black-box in another layout.
Please have a look to the MagCAD documentation for further details.

[Umberto]

Dear Manoj,

your problema is extremely similar to another thread so I will join it.
You could find your answers there.

The error is due to the fact that YOU CAN CONNECT ONLY TWO ADJACENT LAYERS.

Regards,
Umberto

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