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Viewing 8 posts - 31 through 38 (of 38 total)
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  • in reply to: Error in VHDL Simulation of iNML wire #1259
    UmbertoUmberto
    Moderator

    Hi,
    you missed a “;” in your assignment.
    Furthermore a wait statement is needed inside the stimuli process.
    For example:

    A <='1';
    wait for 10 ns;
    A <='0';
    wait for 10 us;
    in reply to: Error in VHDL Simulation using Xilinx ISE #1244
    UmbertoUmberto
    Moderator

    Hi,

    be sure of selecting the proper target in Xilinx ISE. You have to select test and not compiling for the FPGA. “wait statements” are not supported for synthesis but should be fine for simulation.

    Regards,
    Umberto

    in reply to: Error in VHDL Simulation using Xilinx ISE #1241
    UmbertoUmberto
    Moderator

    Hi,

    both the tool should be fine. I’m using Modelsim without any problem. If the error persist, could you please post some details about it?

    Thanks,
    Umberto

    in reply to: vhdl component file is not generated #1218
    UmbertoUmberto
    Moderator

    Hi,

    it is clear from your design that “C” input is on layer 3, while the other magnets lay on layer 0. The input of a Nucleation Center must be on adjacent layers. The basic rules of pNML technology are shown in the MagCAD documentation.

    Keep in mind that the log file in the VHDL folder shows the error that prevent code generation.

    • This reply was modified 6 years, 1 month ago by FabrizioFabrizio.
    • This reply was modified 6 years, 1 month ago by FabrizioFabrizio.
    in reply to: vhdl component file is not generated #1209
    UmbertoUmberto
    Moderator

    Hi,
    did you check the log file in the VHDL folder?
    It would be better if you show your design without the error message.

    Umberto

    in reply to: Unable to generate output waveforms. #1103
    UmbertoUmberto
    Moderator

    Hi,
    we are implementing an automatic area calculation inside the tool. At the moment you can easily compute area occupation considering the higher X and Y coordinates of your design and the area of a single block. For example, referring to the MagCAD Documentation, the minority voter is has a bounding box of 5×5. So you can multiply 25 by the area of a single cell (the default dimension are 350×350 nm) to obtain the “bounding box area”.

    in reply to: Unable to generate output waveforms. #1084
    UmbertoUmberto
    Moderator

    Hi Lavish,

    clock frequency for pNML circuits depends on your layout and it is computed by MagCAD. You can find its value in the definition file inside the VHDL directory (remember to use the correct definition file during simulation).

    Looking at your screenshots i think that simulation time is too small to let you see the correct output. Furthermore, i suggest you to change the time interval among the inputs.
    Please find attached a screenshot of a testbench and the relative waveforms.

    Testbench and waveforms

    I hope this can solve your issue,
    Umberto

    in reply to: Unable to generate output waveforms. #1068
    UmbertoUmberto
    Moderator

    Hi Lavish,

    from your screenshot, it seems that you have selected the wrong file for simulation. In the ISE window, you should include the TestBench file and select that one before clicking “Simulate Behavioral Model”.

    I hope this can solve your issue 🙂

Viewing 8 posts - 31 through 38 (of 38 total)