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Viewing 15 posts - 1 through 15 (of 39 total)
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  • in reply to: Error SUM(0) pin disconnected #2295
    FabrizioFabrizio
    Moderator

    Hello,

    the problem is hidden inside your full adder. You must bring your pins (input/output) at the bounding box edge.
    In your full adder, the input pins are included in the bounding box making it not possible a direct connecting within the same layer.
    Try using the attached one. Remember to replace all the black boxes within the CSA with the new one.

    Best,

    FR

    FabrizioFabrizio
    Moderator

    Dear Raja Sekar,

    unfortunately feedbacks are not supported in iNML designs.

    Best regards.

    Fabrizio

    in reply to: AND GATE #1943
    FabrizioFabrizio
    Moderator

    Dear Rishikesh,

    when you apply inputs to the circuit they get inverted on the ANC.
    It is normal what you get.

    Best regards.

    in reply to: AND GATE #1942
    FabrizioFabrizio
    Moderator

    Dear Rishikesh,

    when you apply inputs to the circuit they get inverted on the ANC.
    It is normal what you get.

    Best regards.

    FabrizioFabrizio
    Moderator

    Dear Rishikesh,

    Within the log file, the user will find the execution time of the main steps of the VHDL generation algorithm, in particular: element translation, connection detection, and function detection. It is not a problem.
    We are updating the documentation to mention also these outputs in the log file.

    FabrizioFabrizio
    Moderator

    Dear Rishikesh,

    we have just released the new version of the tool with the bug fix and some improvement.

    in reply to: Power consumption #1883
    FabrizioFabrizio
    Moderator

    Hello,

    MagCAD doesn’t estimate the power consumption of pNML circuit at the moment. The following discussion can be helpful.
    The bounding box area is reported in the .log file produced during the netlist extraction in MagCADFiles->VHDL-><yourcicuit>.
    The critical path is reported in the definition file as T_eff, which is the sum of the nucleation time (if available) and propagation time.

    Best regards.

    • This reply was modified 2 years, 9 months ago by FabrizioFabrizio.
    in reply to: Input Missing for Cell #1806
    FabrizioFabrizio
    Moderator

    Hi,
    I’m happy to hear that you managed to solve this issue. The tool was complaining for a good reason 🙂

    Regards.

    in reply to: Input Missing for Cell #1802
    FabrizioFabrizio
    Moderator

    Hi,

    I suggest you upload the .qll files (if more than one) of your design. Without them, we cannot understand your issue.
    Anyway, our emails are within the people section.

    Regards.

    in reply to: Simulation error #1762
    FabrizioFabrizio
    Moderator

    Hi,

    you are getting the error to the pad in coordinate x=2, y=3 because you cannot connect to another pad. If you look at the documentation you can find the connectivity options for every element. Why would you couple three pads together? Move forward the two pads around the nucleation center and your issue will be solved.
    Remember also to assign an output pin to the circuit.

    Fabrizio

    • This reply was modified 3 years, 3 months ago by UmbertoUmberto.
    in reply to: Power Calculation #1753
    FabrizioFabrizio
    Moderator

    Hi,

    the main power contribution in pNML is related to the switching field required, the clocking circuitry used and the area that should be irradiated. At the moment, it is not integrated into MagCAD. However, you can have a look at the paper “Towards on-chip clocking of perpendicular Nanomagnetic Logic” from M.Becherer which explains a possible solution to clock pNML circuits.

    Best.

    Fabrizio

    in reply to: Error During Simulating using Xilinx ISE #1743
    FabrizioFabrizio
    Moderator

    Hi,

    you are getting this error because one of the signals is named “sec”, which is a VHDL keyword for seconds.

    Fabrizio

    in reply to: Use Components in MagCAD #1713
    FabrizioFabrizio
    Moderator

    Hi,

    From your layouts I see that full_adder1 in included in full_adder_box. As a consequence, it is normal the second layout is larger, because you added additional interconnection wires. The bounding box is the minimum box that contains the whole layout.
    You con see a summary in the attached picture: bounding_box1 < bounding_box2 as expected.

    Did you mean something different?

    Fabrizio

    Attachments:
    in reply to: Use Components in MagCAD #1706
    FabrizioFabrizio
    Moderator

    Hi,

    I don’t get the point. Can you please upload the .qll files of the 4.18um2 circuit and the 8.1um2?
    In general, the circuit latency depends on the critical path, which is represented by the longest nanowire + nucleation. If a component is inserted in a larger design I would expect that the bounding box area increases.

    Fabrizio

    in reply to: Use Components in MagCAD #1701
    FabrizioFabrizio
    Moderator

    Hi Saurabh,

    we have updated the documentation with a tutorial on hierarchical designs. This should give the basic information required to achieve a fully working hierarchical circuit.
    The hierarchical design is intended to simplify and reduce the complexity of your final architecture re-using existing components.
    As happens with every component, the user has to insert the input and output pins also in the top-level circuit, otherwise the VHDL generation cannot be completed.

    Let me know if documentation can solve your issues.

    • This reply was modified 3 years, 4 months ago by FabrizioFabrizio.
    • This reply was modified 3 years, 4 months ago by FabrizioFabrizio.
Viewing 15 posts - 1 through 15 (of 39 total)