Home › Forums › ToPoliNano Support › HDL Compiler › Parser Error for synopsys DC generated net list VHDL/.v code in ToPoliNano Tagged: Parser This topic has 1 reply, 2 voices, and was last updated 4 years, 1 month ago by Fabrizio. Viewing 2 posts - 1 through 2 (of 2 total) Author Posts September 30, 2020 at 12:47 pm #2219 Raja Sekar KParticipant Error for synopsys DC generated net list VHDL/verilog code in ToPoliNano Parsing failed in file C:/Users/ece/work/MQCAProject/Input_Files/counterVHD.vhd Parser error, aborting compilation How to solve ….. This topic was modified 4 years, 2 months ago by Raja Sekar K. Reason: File not support This topic was modified 4 years, 1 month ago by Fabrizio. Attachments: countervhd.txt netlistCounterVerilog.txt netlistcounterVHDL.txt October 23, 2020 at 6:18 am #2228 FabrizioModerator Dear Raja Sekar, unfortunately feedbacks are not supported in iNML designs. Best regards. Fabrizio Author Posts Viewing 2 posts - 1 through 2 (of 2 total) You must be logged in to reply to this topic. Log In Username: Password: Keep me signed in Log In