Home Forums ToPoliNano Support HDL Compiler Parser Error for synopsys DC generated net list VHDL/.v code in ToPoliNano

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  • #2219
    Raja Sekar KRaja Sekar K
    Participant

    Error for synopsys DC generated net list VHDL/verilog code in ToPoliNano

    Parsing failed in file C:/Users/ece/work/MQCAProject/Input_Files/counterVHD.vhd
    Parser error, aborting compilation

    How to solve …..

    • This topic was modified 1 year ago by Raja Sekar KRaja Sekar K. Reason: File not support
    • This topic was modified 11 months, 3 weeks ago by FabrizioFabrizio.
    #2228
    FabrizioFabrizio
    Moderator

    Dear Raja Sekar,

    unfortunately feedbacks are not supported in iNML designs.

    Best regards.

    Fabrizio

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