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  • September 30, 2020 at 12:47 pm #2219
    Raja Sekar KRaja Sekar K
    Participant

    Error for synopsys DC generated net list VHDL/verilog code in ToPoliNano

    Parsing failed in file C:/Users/ece/work/MQCAProject/Input_Files/counterVHD.vhd
    Parser error, aborting compilation

    How to solve …..

    • This topic was modified 3 years, 6 months ago by Raja Sekar KRaja Sekar K. Reason: File not support
    • This topic was modified 3 years, 6 months ago by FabrizioFabrizio.
    Attachments:
    1. countervhd.txt
    2. netlistCounterVerilog.txt
    3. netlistcounterVHDL.txt
    October 23, 2020 at 6:18 am #2228
    FabrizioFabrizio
    Moderator

    Dear Raja Sekar,

    unfortunately feedbacks are not supported in iNML designs.

    Best regards.

    Fabrizio

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