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Viewing 15 posts - 16 through 30 (of 39 total)
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  • in reply to: General Question #1673
    FabrizioFabrizio
    Moderator

    Dear Saurabh,

    in principle, you can implement any function using majority gate networks. You can use some example majority synthesis tools like ABC or MIG from Epfl. Then you can map the obtained logic network in NML technology.

    in reply to: not able to generate VHDL file. #1623
    FabrizioFabrizio
    Moderator

    Dear Anshul,

    as suggested by the pop-up dialog window, you should read the log file generated during the netlist extraction.
    The message says that there is a connection problem at x: 107, y:34, layer: 0. Just go with your mouse cursor over the correct coordinate and check if you have properly connected the pNML elements.
    For the available connectivity, please have a look at the documentation.

    In case you still have problem please upload the layout file and not the screenshot.

    Best regards.

    Fabrizio

    • This reply was modified 5 years, 4 months ago by FabrizioFabrizio.
    in reply to: ERROR: node function unset #1566
    FabrizioFabrizio
    Moderator

    Dear Ali,

    we are working on that. It will be available in the next months.

    in reply to: ERROR: node function unset #1557
    FabrizioFabrizio
    Moderator

    Dear Ali,

    as I wrote in your previous post only some basic gates with specific naming are supported by the iNML technology.
    If you look at the documentation, you can see the following table that summarized what you should know.
    Let me know if everything is clear. The generated error means that “orgate” and “andgate” are unknown gate names.

    • This reply was modified 5 years, 9 months ago by FabrizioFabrizio.
    • This reply was modified 5 years, 9 months ago by FabrizioFabrizio.
    Attachments:
    in reply to: parser error #1543
    FabrizioFabrizio
    Moderator

    Dear Ali,

    the HDL parser can accept only structural/post-synthesis VHDL description. This means that for each used gate the corresponding component should be declared within the architecture. ToPoliNano is not a synthesis tool. It takes the nestist and perform the physical design.
    In your specific case, the declaration of the XOR gate is missing. However, I would suggest using ONLY the 4 gates supported by the iNML technology as reported in the ToPoliNano documentation, which are:
    – AND
    – OR
    – INV
    – MV

    in reply to: ToPoliNano Import #1494
    FabrizioFabrizio
    Moderator

    Dear Peyman,

    we just released the 1.0.2 version of ToPoliNano fixing the issue.

    • This reply was modified 5 years, 10 months ago by FabrizioFabrizio.
    in reply to: ToPoliNano Import #1436
    FabrizioFabrizio
    Moderator

    Hi,

    you should right-click on the testbench file and click on “set testbench” before running the simulation. You can have a look to the ToPoliNano documentation for more detail.

    in reply to: Parameters Query #1414
    FabrizioFabrizio
    Moderator

    Dear Saurabh,

    in the model, you set the nucleation probability accepted. That probability is computed at every step during the simulation. It depends on different parameters among which the effective coupling on the ANC.
    You can find additional info on this paper

    • This reply was modified 6 years ago by FabrizioFabrizio.
    • This reply was modified 6 years ago by FabrizioFabrizio.
    in reply to: optimizing logic gates #1399
    FabrizioFabrizio
    Moderator

    Dear Peyman,

    you can have a look at the MagCad’s user guide available on the documentation page.

    Fabrizio

    in reply to: iNML file(.vhdl) not able to run behavioral code #1390
    FabrizioFabrizio
    Moderator

    Dear Divyang,

    your are trying to compile the “entity file”, which doesn’t contain useful information for the simulation. It should not be used as explained within the user guide.
    The required files for the iNML simulation are:
    – <circuit_name>.vhd
    – library_pnml.vhd
    – <circuit_name>_TB.vhd

    Fabrizio

    • This reply was modified 6 years ago by FabrizioFabrizio.
    in reply to: circuit is not behaving properly #1375
    FabrizioFabrizio
    Moderator

    Dear Rashmishree,

    could you please upload the .qll file of your design?
    Thanks.

    Fabrizio

    in reply to: Calculate the bounding area and extract critical path #1296
    FabrizioFabrizio
    Moderator

    Dear Rashmishr,

    both parameters are automatically extracted by MagCAD. The bounding box area is saved within the log file generated during the netlist extraction (see the documentation).
    The critical path instead, is saved within the definition file, because it is required for the simulation phase.

    Fabrizio

    in reply to: Calculating the area #1269
    FabrizioFabrizio
    Moderator

    Dear Chinmay,

    since version 2.2.0, the bounding box area is automatically computed by MagCAD and saved within the log file generated during the VHDL netlist extraction.

    in reply to: vhdl component file is not generated #1233
    FabrizioFabrizio
    Moderator

    Dear Bandan,

    your log file reports that there is no possible connection for input pin (b) at coordinate x=-1, y=2, layer=0.
    Probably you placed the input pin (b) on layer 0 instead of layer 1. Moving it to the upper layer should solve your issue.

    in reply to: Reducing the Latency #1213
    FabrizioFabrizio
    Moderator

    Dear Chinmay,

    the total latency related to the number of ANC to be crossed. In principle, to reduce the latency you should reduce the number of gates. Another possibility is to synchronize the two outputs by adding some delays on the fastest path.

    Fabrizio

Viewing 15 posts - 16 through 30 (of 39 total)