Home Forums MagCAD Support HDL Models Error in VHDL Simulation using Xilinx ISE

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  • #1239
    Bandan BhoiBandan Bhoi
    Participant

    Sir,

    For VHDL file simulation Xilinx ISE tool is compatible or not. Because i am getting syntax error. Kindly suggest me to go with this tool or should i go for modelsim.

    Thanking you

    • This topic was modified 3 years, 10 months ago by UmbertoUmberto. Reason: Moved to the correct Forum
    • This topic was modified 3 years, 9 months ago by FabrizioFabrizio.
    #1241
    UmbertoUmberto
    Moderator

    Hi,

    both the tool should be fine. I’m using Modelsim without any problem. If the error persist, could you please post some details about it?

    Thanks,
    Umberto

    #1242
    Bandan BhoiBandan Bhoi
    Participant

    Sir,

    In library_pNML vhdl file on below line it is showing the error

    wait for T_propagation * 1 sec

    error message is — Wait for statement unsupported

    Requesting you to Kindly guide me on this.

    Thanking you

    #1244
    UmbertoUmberto
    Moderator

    Hi,

    be sure of selecting the proper target in Xilinx ISE. You have to select test and not compiling for the FPGA. “wait statements” are not supported for synthesis but should be fine for simulation.

    Regards,
    Umberto

    #1260
    Bandan BhoiBandan Bhoi
    Participant

    sir,
    I have generated VHDL code for the two input XOR gate. Below is the test bench code of the xor gate. I have also attached the figure of waveform.It is showing Unknown value U for clk and output O.

    test bench file-

    
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use work.components_pnml.all;
    use work.definitions_pnml.all;
    
    entity tb_pNML_custom_XORNEW is
    end tb_pNML_custom_XORNEW;
    
    architecture Behavioural of tb_pNML_custom_XORNEW is
    
    signal CLK : std_logic;
    signal O :std_logic;
    signal O_param : param_data := (others => 0.0);
    signal X :std_logic;
    signal X_param : param_data := (others => 0.0);
    signal Y :std_logic;
    signal Y_param : param_data := (others => 0.0);
    
    component pNML_custom_XORNEW is
    port(
    	O: out std_logic;
    	O_param: out param_data := (others => 0.0);
    	X: in std_logic;
    	X_param: in param_data := (others => 0.0);
    	Y: in std_logic;
    	Y_param: in param_data := (others => 0.0);
    	CLK: in std_logic);
    end component;
    
    begin
    
    DUT : pNML_custom_XORNEW port map(O => O, O_param => O_param, 
    X => X, X_param => X_param, 
    Y => Y, Y_param => Y_param, 
    CLK => CLK);
    
     clock_proc:process
     begin
     CLK<='1';
      wait for t_clock * 1 sec;
      CLK<='0';
      wait for t_clock * 1 sec;
    end process clock_proc; 
      clk <= not clk after 10 ns;
    input_proc: process
    begin
     --insert your input stimuli here 
    
    X<='0';
    wait for t_clock * 1 sec;
    Y<='1';
    wait for t_clock * 1 sec;
    end process input_proc;
    
    end Behavioural;
    
    • This reply was modified 3 years, 9 months ago by FabrizioFabrizio. Reason: please use the code tag when posting vhdl code
    Attachments:
    #1273
    UmbertoUmberto
    Moderator

    Hi,
    the clock process in your testbench is incorrect. Please use the template automatically generated by the tool and modify only the input stimuli process. Furthermore, the wait statement in the input process should be a little longer, and check to simulate for enough time in order to get output value.

    Regards,
    Umberto

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