Home Forums MagCAD Support HDL Models Unable to generate output waveforms.

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  • #1053
    lavish jainlavish jain
    Participant

    Hello everyone,
    I am new to MagCAD tool and I am following the documentation available on the website. I have successfully generated the VHDL codes for pNML XOR gate. Now I want to verify whether my design is correct.For this purpose, I referred the MagCAD tutorial but I am not able to understand the changes to be made to generate the output waveforms. Kindly explain the procedure to validate the design.
    Please find attached the screenshots of the changes in testbench and corresponding outputs.

    Output waveforms.
    Testbench behavioral code

    • This topic was modified 3 years, 11 months ago by FabrizioFabrizio.
    • This topic was modified 3 years, 9 months ago by FabrizioFabrizio. Reason: the technology used is pNML and not iNML
    #1068
    UmbertoUmberto
    Moderator

    Hi Lavish,

    from your screenshot, it seems that you have selected the wrong file for simulation. In the ISE window, you should include the TestBench file and select that one before clicking “Simulate Behavioral Model”.

    I hope this can solve your issue 🙂

    #1082
    lavish jainlavish jain
    Participant

    Hi Umberto,
    Thank you for your response. As per your suggestion, I selected the TestBench file before simulation of pNML OR gate design. For this, the waveforms are correctly generated for inputs A and B, but the output Y is indicated as “Uninitialized”(highlighted in red) and remains the same for all input combinations. Please find attached the screenshots of both the TestBench code and the output waveforms.

    OR Gate Output Waveforms
    OR Gate TestBench Code

    Kindly suggest me some way to deal with this issue. It would be of great help if you attach some example files and screenshots to explain the steps to verify the design by generating waveforms.

    Thank you,
    Lavish Jain

    • This reply was modified 3 years, 11 months ago by lavish jainlavish jain.
    #1084
    UmbertoUmberto
    Moderator

    Hi Lavish,

    clock frequency for pNML circuits depends on your layout and it is computed by MagCAD. You can find its value in the definition file inside the VHDL directory (remember to use the correct definition file during simulation).

    Looking at your screenshots i think that simulation time is too small to let you see the correct output. Furthermore, i suggest you to change the time interval among the inputs.
    Please find attached a screenshot of a testbench and the relative waveforms.

    Testbench and waveforms

    I hope this can solve your issue,
    Umberto

    #1086
    lavish jainlavish jain
    Participant

    Hi Umberto,

    Thanks a lot for your fast response and support. Now, I am able to generate and analyze the output waveforms and other parameters. I am following the paper “MagCAD: Tool for the Design of 3-D Magnetic Circuits” and there is one parameter called “bounding box area” mentioned in the paper. I have gone through the paper several times but I am not able to figure out the procedure to calculate the area. It would be of great help if you could help me with this parameter.

    Thank you,
    Lavish

    #1103
    UmbertoUmberto
    Moderator

    Hi,
    we are implementing an automatic area calculation inside the tool. At the moment you can easily compute area occupation considering the higher X and Y coordinates of your design and the area of a single block. For example, referring to the MagCAD Documentation, the minority voter is has a bounding box of 5×5. So you can multiply 25 by the area of a single cell (the default dimension are 350×350 nm) to obtain the “bounding box area”.

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