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Viewing 11 posts - 1 through 11 (of 11 total)
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  • in reply to: General Question #1755
    Saurabh KumarSaurabh Kumar
    Participant

    Hi,
    I recently came across this question “How can you say that the M(A,B,C) is AB+BC+CA”? I believe that we need to use MIGs to reduce the expression to majority but I am finding it difficult to arrive at the solution. I went through the paper titled “Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization” by Luca Amaru where algorithms and rules have been listed but somehow still I have not been able to arrive at the answer. Can you help me with this reduction process step by step.
    Hoping to hear from you soon,
    Saurabh

    ## Update: I solved it. Thank you.

    in reply to: Error During Simulating using Xilinx ISE #1740
    Saurabh KumarSaurabh Kumar
    Participant

    Please find attached the files.

    Thanks
    Saurabh

    in reply to: Input Missing for Cell #1733
    Saurabh KumarSaurabh Kumar
    Participant

    These are the screenshots

    in reply to: Input Missing for Cell #1732
    Saurabh KumarSaurabh Kumar
    Participant

    Hi,
    Although I corrected the error, this seems to something unusual. I have attached the screenshot. Can you please explain?

    in reply to: Use Components in MagCAD #1728
    Saurabh KumarSaurabh Kumar
    Participant

    Yes,
    I get it now. The mistake I was doing was, I was comparing the flat design(normal) with the bounding box design.
    The design with bounding box will definitely have larger area and latency but that will be equal to the flat design of the bounding box.
    Well,
    Thank you very much for your continuous support.
    Saurabh

    in reply to: Use Components in MagCAD #1715
    Saurabh KumarSaurabh Kumar
    Participant

    Hi,
    I get that the area will definitely increase. No doubt at that part. But here what I want to say:

    The main use of hierarchical method is to reduce circuit complexity without changing its area and latency (Correct me if I am wrong here).
    The area will increase because I am adding extra wires, BUT THE LATENCY SHOULD NOT CHANGE WHILE WE USE HIERARCHICAL METHOD while in the above case, the latency also increases while we use the HIERARCHICAL METHOD. I am expecting that the LATENCY SHOULD NOT CHANGE.

    Is it that when we will use HIERARCHICAL METHOD the latency and area will increase? If yes, then it is better to design the circuit without HIERARCHICAL METHOD because ultimately we want reduced area and delay.

    in reply to: Use Components in MagCAD #1707
    Saurabh KumarSaurabh Kumar
    Participant

    Hi. Please find attached the .qll file for both the adders.
    Thanks

    in reply to: Use Components in MagCAD #1705
    Saurabh KumarSaurabh Kumar
    Participant

    Hi,
    Thanks. IT WORKS!!!!.
    Still I feel not satisfied. Reason being, When I use the concept of Black Box and implement, the area and latency increases. If I don’t use the black box concept, the area and latency is reduced.

    Example an full adder without the black box thing occupies area of 4.18 um2 whereas with the black_box it occupies an area of 8.1um2.

    I get the thing that the area will definitely increase because we are adding inputs, wires, and outputs.

    But would’t it be better that the area/latency shouldn’t increase. We use the concept of hierarchical method to ease our designing part but if this is at the cost of area and latency, it wouldn’t justify.

    OR

    when we implement this physically, the area and latency will be reduced (as compared to hierarchical method) irrespective of the design and latency shown in simulation(of hierarchical method) ?

    Thanks,
    Saurabh

    in reply to: Use Components in MagCAD #1692
    Saurabh KumarSaurabh Kumar
    Participant

    Hi,
    I get that the tool will generate different VHDL automatically. And although I am connecting two adders using magnets, it still shows the error that input is missing.
    Another Query is that do the output of one full adder and input for the next full adder should have the same variable name?(In case of RCA.
    Please can you demonstrate this using one full adder and implementing a 4-BIT RCA.
    Thanks.

    in reply to: Use Components in MagCAD #1686
    Saurabh KumarSaurabh Kumar
    Participant

    I am attaching the QCA file for the full adder and 4 bit RCA file also. full_adder1, full_adder2 etc. are adders I intend to use. Because the limit is 4 files, I couldn’t attach the 4th.
    Hope to hear soon from you.

    in reply to: Use Components in MagCAD #1684
    Saurabh KumarSaurabh Kumar
    Participant

    Hi,
    I went through the documentation but couldn’t gather much support from it. I am able to bring 4 full adders( I plan to design 4 bit RCA) but I don’t know how to connect them. I have attached screenshot for that.

    Also, how will the inputs vary. In the full adder design, the inputs are A, B, and Cin. and this seems to be same for all the adders. In general the inputs are (A0,B0,Cin) then (A1,B1,Carry1) etc.

    I request you to please guide me, and if possible, can you make a small video on “how to use a component as black box”.
    That would be a great help not just for me but for others as well.

    Thanks

    Attachments:
Viewing 11 posts - 1 through 11 (of 11 total)