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  • in reply to: i-NML Technology problem in running the file #1749
    Divyang ThakkarDivyang Thakkar
    Participant

    Sir,
    I am attaching here .qll file for reference.

    Attachments:
    in reply to: iNML file(.vhdl) not able to run behavioral code #1418
    Divyang ThakkarDivyang Thakkar
    Participant

    Yes, Sir you were right. I have rectified that error and now it is working fine.

    In my design of Compressor, I need to input 0 at certain places when I am doing it I am getting error while uploading the necessary files.

    The error reads as:

    
    INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" into library work
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 61: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 62: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 65: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 66: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 95: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 96: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 97: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 98: Syntax error near "0".
    INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" into library work
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 69: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 70: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 73: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 74: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 101: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 102: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 103: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 104: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 460: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 461: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 464: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 465: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 494: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 495: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 496: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 497: Syntax error near "0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 834: Syntax error near "=>".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 836: Syntax error near "=>".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 850: Syntax error near "=>".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 851: Syntax error near "=>".
    INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/library_inml.vhd" into library work
    ERROR:ProjectMgmt - 28 error(s) found while parsing design hierarchy.
    

    Sir can you please guide me on how to input 0 in iNML technology.

    • This reply was modified 5 years, 12 months ago by FabrizioFabrizio. Reason: Please use code tags when posting log messages
    in reply to: iNML file(.vhdl) not able to run behavioral code #1410
    Divyang ThakkarDivyang Thakkar
    Participant

    Sir can you please elaborate on how can I use code tags to add vhdl codes or log messages

    One more thing I am not getting the following file:

    library_pnml.vhd

    I am working on iNML technology then why do we need to add the pnml file?

    in reply to: iNML file(.vhdl) not able to run behavioral code #1405
    Divyang ThakkarDivyang Thakkar
    Participant

    I am creating a Half Adder which has 2 inputs: X0 and X1.
    After Exporting the HalfAdder.qll file I am not getting the library_pnml.vhd file in the VHDL folder; Althought he export was successful and the vhdl file was generated.

    On Including the files:
    – <circuit_name>.vhd
    – library_inml.vhd
    – <circuit_name>_TB.vhd
    And giving the test bench input for HalfAdder file I am getting the following error:

    INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/HalfAdder/HalfAdder_TB.vhd" into library work
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/HalfAdder/HalfAdder_TB.vhd" Line 88: Syntax error near "X0".
    ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/HalfAdder/HalfAdder_TB.vhd" Line 89: Syntax error near "'".
    ERROR:ProjectMgmt - 2 error(s) found while parsing design hierarchy.

    The Input Test Bench is as follows:

    --insert your input stimuli here 
    
    wait for 10us;
    
    assign X0<=1'b0;
    assign X1<=1'b1;
    • This reply was modified 6 years ago by FabrizioFabrizio. Reason: Please use code tags to add vhdl code or log messages
    Attachments:
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