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  • in reply to: Error in VHDL Simulation using Xilinx ISE #1260
    Bandan BhoiBandan Bhoi
    Participant

    sir,
    I have generated VHDL code for the two input XOR gate. Below is the test bench code of the xor gate. I have also attached the figure of waveform.It is showing Unknown value U for clk and output O.

    test bench file-

    
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use work.components_pnml.all;
    use work.definitions_pnml.all;
    
    entity tb_pNML_custom_XORNEW is
    end tb_pNML_custom_XORNEW;
    
    architecture Behavioural of tb_pNML_custom_XORNEW is
    
    signal CLK : std_logic;
    signal O :std_logic;
    signal O_param : param_data := (others => 0.0);
    signal X :std_logic;
    signal X_param : param_data := (others => 0.0);
    signal Y :std_logic;
    signal Y_param : param_data := (others => 0.0);
    
    component pNML_custom_XORNEW is
    port(
    	O: out std_logic;
    	O_param: out param_data := (others => 0.0);
    	X: in std_logic;
    	X_param: in param_data := (others => 0.0);
    	Y: in std_logic;
    	Y_param: in param_data := (others => 0.0);
    	CLK: in std_logic);
    end component;
    
    begin
    
    DUT : pNML_custom_XORNEW port map(O => O, O_param => O_param, 
    X => X, X_param => X_param, 
    Y => Y, Y_param => Y_param, 
    CLK => CLK);
    
     clock_proc:process
     begin
     CLK<='1';
      wait for t_clock * 1 sec;
      CLK<='0';
      wait for t_clock * 1 sec;
    end process clock_proc; 
      clk <= not clk after 10 ns;
    input_proc: process
    begin
     --insert your input stimuli here 
    
    X<='0';
    wait for t_clock * 1 sec;
    Y<='1';
    wait for t_clock * 1 sec;
    end process input_proc;
    
    end Behavioural;
    
    • This reply was modified 4 years, 6 months ago by FabrizioFabrizio. Reason: please use the code tag when posting vhdl code
    Attachments:
    in reply to: Error in VHDL Simulation using Xilinx ISE #1242
    Bandan BhoiBandan Bhoi
    Participant

    Sir,

    In library_pNML vhdl file on below line it is showing the error

    wait for T_propagation * 1 sec

    error message is — Wait for statement unsupported

    Requesting you to Kindly guide me on this.

    Thanking you

    in reply to: vhdl component file is not generated #1226
    Bandan BhoiBandan Bhoi
    Participant

    sir,
    in my previous post figure is not attached. Here i am attaching the figure.
    Thanking you

    in reply to: vhdl component file is not generated #1225
    Bandan BhoiBandan Bhoi
    Participant

    sir,
    In pNML minority voter circuit vhdl file is not generating. This is log file generated.

    Log of compilation, 01/02/2018 – 17:07:48
    Process starts.
    14 vhdl items created.
    Output match not found for cell -1-2-0

    I am requesting you to kindly give the solution.
    Thanking you

    • This reply was modified 4 years, 6 months ago by FabrizioFabrizio.
    • This reply was modified 4 years, 6 months ago by FabrizioFabrizio.
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