Parser Error for synopsys DC generated net list VHDL/.v code in ToPoliNano

[Raja Sekar K]

Error for synopsys DC generated net list VHDL/verilog code in ToPoliNano

Parsing failed in file C:/Users/ece/work/MQCAProject/Input_Files/counterVHD.vhd
Parser error, aborting compilation

How to solve …..

• This topic was modified 5 years, 3 months ago by Raja Sekar K. Reason: File not support
• This topic was modified 5 years, 2 months ago by Fabrizio.

Attachments:

1. countervhd.txt
2. netlistCounterVerilog.txt
3. netlistcounterVHDL.txt

[Fabrizio]

Dear Raja Sekar,

unfortunately feedbacks are not supported in iNML designs.

Best regards.

Fabrizio

[Author]

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