Home › Forums › MagCAD Support › HDL Models › Error : VHDL files not generated This topic has 0 replies, 1 voice, and was last updated 8 months, 2 weeks ago by Venkata Chandrahasa Chilukuri. Viewing 1 post (of 1 total) Author Posts March 23, 2024 at 7:23 am #28172 Venkata Chandrahasa ChilukuriParticipant I am trying to implement full adder circuit. The problem is that I am unable to get the VHDL code due to an error I had another doubt : Can I run the VHDL code on Vivado? Thank you This topic was modified 8 months, 2 weeks ago by Venkata Chandrahasa Chilukuri. Attachments:Screenshot-2024-03-23-123047.png FA3D_pnml.qcc Author Posts Viewing 1 post (of 1 total) You must be logged in to reply to this topic. Log In Username: Password: Keep me signed in Log In