Hi,
I am also using Xilinx ISE for simulation of the VHDL netlist. I am also not getting the same output as the one shown in the paper. Also, I wanted to know how to change the t_clock. Every time I export the VHDL code, a definition_pnml.vhd file is generated. When trying to simulate a design do we have to use the file specific to the design or is it fine if we use a general definition_pnml.vhd file. Like for example if I generate a VHDL file for full adder, can I use that definition_pnml.vhd file for a minority voter? or do I have to use the minority voter definition_pnml.vhd file?
