Sir
I am making a digital circuit for the project I have been working on
but there is some error in the circuit as vhdl file is not been generated
I checked the cells in the design where error was showing ( in log file) but there is NOTHING WRONG THAT I CAN FIGURE OUT.
Please help!
ERROR MESSAGE:
Input missing for cells x: 124, y: 52, Layer: 2
Input missing for cells x: 124, y: 49, Layer: 1
Input missing for cells x: 133, y: 54, Layer: 2
Input missing for cells x: 133, y: 51, Layer: 1
Input missing for cells x: 142, y: 56, Layer: 2
Input missing for cells x: 142, y: 53, Layer: 1
Also can we connect layer 0 to layer 2 0r layer 3 directly or do we have to go through layer 1 first.
i have circled the issue in the screenshots and also uploaded .qll file
THANK YOU