consider to always attach the qll, it is the best way to see where the problem is.
Going back to your problem, you are connecting a layer 0 via to a layer 3 Nucleation. The coordinates that you can read in the log are the one of the qcc. The layout is always “moved” to the top left corner before generating the qcc and the VHDL.
Another problem in your layout, should be just warnings, are the pad unconnected. Consider vias as “T” connection to another plane. If you need just to connect the other layer and terminate the line you can use the pad. The example shows what I’m saying.