Home › Forums › MagCAD Support › HDL Models › Error in VHDL Simulation using Xilinx ISE › Reply To: Error in VHDL Simulation using Xilinx ISE February 7, 2018 at 9:07 am #1244 UmbertoModerator Hi, be sure of selecting the proper target in Xilinx ISE. You have to select test and not compiling for the FPGA. “wait statements” are not supported for synthesis but should be fine for simulation. Regards, Umberto
