some portions of the generated definition_pnml.vhd are strictly related to the design. As a consequence, you should use the generated “definition” files to simulate your circuit.
The minimum t_clock is automatically computed by the tool during the VHDL netlist extraction, according to the compact model associated to the technology. If you want to change it you can find it within the definition file. Keep in mind that reducing too much t_clock the circuit would not work properly.
I hope I have clarified your doubts.