clock frequency for pNML circuits depends on your layout and it is computed by MagCAD. You can find its value in the definition file inside the VHDL directory (remember to use the correct definition file during simulation).
Looking at your screenshots i think that simulation time is too small to let you see the correct output. Furthermore, i suggest you to change the time interval among the inputs.
Please find attached a screenshot of a testbench and the relative waveforms.
I hope this can solve your issue,