Hi Umberto,
Thank you for your response. As per your suggestion, I selected the TestBench file before simulation of pNML OR gate design. For this, the waveforms are correctly generated for inputs A and B, but the output Y is indicated as “Uninitialized”(highlighted in red) and remains the same for all input combinations. Please find attached the screenshots of both the TestBench code and the output waveforms.
OR Gate Output Waveforms
OR Gate TestBench Code
Kindly suggest me some way to deal with this issue. It would be of great help if you attach some example files and screenshots to explain the steps to verify the design by generating waveforms.
Thank you,
Lavish Jain