Home › Forums › MagCAD Support › HDL Models › Error in VHDL Simulation using Xilinx ISE › Reply To: Error in VHDL Simulation using Xilinx ISE February 6, 2018 at 5:46 pm #1242 Bandan BhoiParticipant Sir, In library_pNML vhdl file on below line it is showing the error wait for T_propagation * 1 sec error message is — Wait for statement unsupported Requesting you to Kindly guide me on this. Thanking you
