[Chinmay Joshi]

Hi Fabrizio,

Thanks for the help. I got the output now.

[Chinmay Joshi]

With the above design, all the outputs are coming wrong except when all inputs are 0

[Chinmay Joshi]

Hi Fabrizio,

Here is my circuit for half adder using minority NAND configuration. I am still getting the wrong output.

Attachments:

1. 

   half-adder1.jpg
   

2. 

   half-adder-waveform1.jpg
   

[Chinmay Joshi]

Hi Fabrizio,

Sorry I read that reversing of the inputs now. I got to know why my output wasn’t coming. Thanks for clearing my doubt.

[Chinmay Joshi]

The output waveform is for the input a=1 b=1 c=0

Attachments:

1. 

   2D-minority-waveform.jpg
   

2. 

   2D-minority-1.jpg
   

[Chinmay Joshi]

Hi Fabrizio,

Thanks for clearing my doubt. I have another problem. When I try the minority voter circuit in MagCAD, the output comes that of a majority voter. This is true for the 2D voter. But in the case of 3D minority voter a random output sequence is generated. Same happens when I try to implement full adder. I guess it uses the majority voter principle.

[Chinmay Joshi]

Hi,

I am also using Xilinx ISE for simulation of the VHDL netlist. I am also not getting the same output as the one shown in the paper. Also, I wanted to know how to change the t_clock. Every time I export the VHDL code, a definition_pnml.vhd file is generated. When trying to simulate a design do we have to use the file specific to the design or is it fine if we use a general definition_pnml.vhd file. Like for example if I generate a VHDL file for full adder, can I use that definition_pnml.vhd file for a minority voter? or do I have to use the minority voter definition_pnml.vhd file?

Attachments:

1. 

   2D-minority.jpg
   

2. 

   3D-minority.jpg
   

1. Output-table.xlsx

[Author]

Posts