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  • in reply to: not able to generate VHDL file. #1636
    Anshul DalalAnshul Dalal
    Participant

    I will make the changes in my layout as per your suggestions and let you know what happens next.
    I had already attached the ‘.qll’ file in my earlier post but I’ll post it once again.

    in reply to: not able to generate VHDL file. #1633
    Anshul DalalAnshul Dalal
    Participant

    Screenshot

    in reply to: not able to generate VHDL file. #1631
    Anshul DalalAnshul Dalal
    Participant

    As you had pointed, I have flipped the output cell by 180 degrees. But it did not solve the error.

    The log file mentioned error at x=132, y=32, layer=0. I deleted the item and placed a new item. Even then I was getting the error at the same coordinates. I’ve also included the error location in screenshot

    I closed all files and restarted MagCAD and generated log file for the same schematic. Now the error was at x: 107, y: 34, Layer: 0

    I have tried my best to find out the error but nothing appears to be wrong with both these locations.

    Attachments:
    in reply to: not able to generate VHDL file. #1627
    Anshul DalalAnshul Dalal
    Participant

    I had already attached the pdf file in the question too.
    I have a couple of doubts too.

    1. Does MagCAD work fine when working with complex circuit involving more than ‘2’ layers?

    2. Is it valid to take input from an upper layer to the lower layer using ‘Via’ QCA item? I have attached a screenshot below and encircled the cells in which I have used ‘Via’ to take input in a different layer. Please let me know if there is some error in my schematic.

    • This reply was modified 6 years, 1 month ago by Anshul DalalAnshul Dalal.
    in reply to: not able to generate VHDL file. #1625
    Anshul DalalAnshul Dalal
    Participant

    Thank you for replying.
    I am attaching herewith the layout file I am getting error.

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