vhdl component file is not generated

[RASHMISHREE ROUT]

it’s showing error while generating the vhdl file of a 3-D minority votor. after completion of the design part export component is also carried out successfully.

Attachments:

1. 

   error.png
   

[Umberto]

Hi,
did you check the log file in the VHDL folder?
It would be better if you show your design without the error message.

Umberto

[RASHMISHREE ROUT]

I am trying to design a 3-d majority votor in MagCAD. After completing the design part, export component is also showing successful but vhdl file is not generating as i have mentioned in my previous post. Here is the design.

Attachments:

1. 

   minority-votor.png
   

[Umberto]

Hi,

it is clear from your design that “C” input is on layer 3, while the other magnets lay on layer 0. The input of a Nucleation Center must be on adjacent layers. The basic rules of pNML technology are shown in the MagCAD documentation.

Keep in mind that the log file in the VHDL folder shows the error that prevent code generation.

• This reply was modified 8 years ago by Fabrizio.
• This reply was modified 8 years ago by Fabrizio.

[Bandan Bhoi]

sir,
In pNML minority voter circuit vhdl file is not generating. This is log file generated.

Log of compilation, 01/02/2018 – 17:07:48
Process starts.
14 vhdl items created.
Output match not found for cell -1-2-0

I am requesting you to kindly give the solution.
Thanking you

• This reply was modified 8 years ago by Fabrizio.
• This reply was modified 8 years ago by Fabrizio.

[Bandan Bhoi]

sir,
in my previous post figure is not attached. Here i am attaching the figure.
Thanking you

Attachments:

1. 

   3d-minority-voter.png
   

[Fabrizio]

Dear Bandan,

your log file reports that there is no possible connection for input pin (b) at coordinate x=-1, y=2, layer=0.
Probably you placed the input pin (b) on layer 0 instead of layer 1. Moving it to the upper layer should solve your issue.

[Author]

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