Home Forums ToPoliNano Support Simulation ToPoliNano Import

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  • #1429
    peyman safiripeyman safiri
    Participant

    hi , I want to import vhd code from MagCAD into Topolinano , but I can’t compile it and topolinano parser shows error , I atached the screenshot .

    Attachments:
    #1431
    UmbertoUmberto
    Moderator

    Dear Peyman,

    MagCAD vhdl files are not valuable description for ToPoliNano.
    You can use that vhdl to simulate your design with standard HDL simulator (modelsim for example).
    If you want to simulate your design with ToPoliNano you can import the layout directly:
    -file->import layout
    -select from disk the “.qll” file you want to open.
    -simulate it providing a valid testbench.

    Please, consider that the automatic testbench generated by MagCAD is not valid for ToPoliNano. You should remove all the clock processes to use it inside ToPoliNano.

    Umberto

    #1434
    peyman safiripeyman safiri
    Participant

    Hi , I imported my layout and testbench without clock proccess, but when I click on simulate log message say “Select an input waveform”
    I atachetd the screenshot

    Attachments:
    #1436
    FabrizioFabrizio
    Moderator

    Hi,

    you should right-click on the testbench file and click on “set testbench” before running the simulation. You can have a look to the ToPoliNano documentation for more detail.

    #1444
    peyman safiripeyman safiri
    Participant

    hi , I atached my testbench and screenshot from parser erros in topoli nano

    Attachments:
    #1446
    peyman safiripeyman safiri
    Participant

    my testbench code :

    --------------------------------------------------------------------------------
    -- Testbench automatically generated by MagCAD                         --
    -- Date: 15/04/2018                                                           --
    -- Time: 22:27:17                                                             --
    --------------------------------------------------------------------------------
    -- Entity: iNML/xor1/xor
    --------------------------------------------------------------------------------
    -- DO NOT MODIFY THIS TB, EXEPT THE INPUT STIMULI PROCESS
    --------------------------------------------------------------------------------
    
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use work.NML_definitions.all;
    use work.NML_components.all;
    
    entity tb_iNML_xor1_xor is
    GENERIC
    	(
    		phases: natural := 3;
    		period: time	:= 10 ns
    	);
    end tb_iNML_xor1_xor;
    
    architecture Behavioural of tb_iNML_xor1_xor is
    
    signal A :std_logic;
    signal A_param : param_data := (others => 0.0);
    signal BN :std_logic;
    signal BN_param : param_data := (others => 0.0);
    signal B :std_logic;
    signal B_param : param_data := (others => 0.0);
    signal NA :std_logic;
    signal NA_param : param_data := (others => 0.0);
    signal xorout :std_logic;
    signal xorout_param : param_data := (others => 0.0);
    
    component iNML_xor1_xor is
    port(
    	A: in std_logic;
    	A_param: in param_data := (others => 0.0);
    	BN: in std_logic;
    	BN_param: in param_data := (others => 0.0);
    	B: in std_logic;
    	B_param: in param_data := (others => 0.0);
    	NA: in std_logic;
    	NA_param: in param_data := (others => 0.0);
    	xorout: out std_logic;
    	xorout_param: out param_data := (others => 0.0);
    	
    end component;
    
    begin
    
    DUT : iNML_xor1_xor port map(A => A, A_param => A_param, 
    BN => BN, BN_param => BN_param, 
    B => B, B_param => B_param, 
    NA => NA, NA_param => NA_param, 
    xorout => xorout, xorout_param => xorout_param);
    
      
    --------------------------------------------------------------------------------
    -- PLEASE, DO NOT MODIFY BEFORE THIS POINT
    -- USE THIS PROCESS TO INSERT INPUT STIMULI
    -- Please use the following example as a reference:
    -- input_proc: process
    -- begin
    -- in1<='0';
    -- in2<='0';
    -- wait for 30 ns;
    -- in1<='0';
    -- in2<='1';
    -- wait for 30 ns;
    -- in1<='1';
    -- in2<='1';
    -- wait for 30 ns;
    -- in1<='1';
    -- in2<='0';
    -- wait for 100 us;
    -- process input_proc;
    --
    --
    --------------------------------------------------------------------------------
    
    input_proc: process
    begin
     --insert your input stimuli here 
     
     BN <='0';
     B <='1';
     NA <='0';
     A <='1';
     wait for 50 ns;
     BN <='1';
     B <='0';
     NA <='0';
     A <='1';
     wait for 50 ns;
    
    end process input_proc;
    
    end Behavioural;
    • This reply was modified 3 years, 7 months ago by FabrizioFabrizio. Reason: Please paste code within code tags
    #1447
    UmbertoUmberto
    Moderator

    Dear Peyman,

    there was a bug in the import method preventing correct simulation. The next release of MagCAD will solve the issue. Please update the tool as soon as the update is released, and generate again the component to get also a template of testbench compatible with ToPoliNano.

    Umberto

    #1475
    peyman safiripeyman safiri
    Participant

    hi , I updated magcad software and exported topolinano testbench but another erroe apeared , I atached my testbench and screenshot.
    my testbench :

    --------------------------------------------------------------------------------
    -- Testbench automatically generated by MagCAD                         --
    -- Date: 02/05/2018                                                           --
    -- Time: 13:07:21                                                             --
    --------------------------------------------------------------------------------
    -- Entity: iNML/xor/xor
    --------------------------------------------------------------------------------
    -- DO NOT MODIFY THIS TB, EXCEPT THE INPUT STIMULI PROCESS
    --------------------------------------------------------------------------------
    
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    
    entity tb_iNML_xor_xor is
    end tb_iNML_xor_xor;
    
    architecture Behavioural of tb_iNML_xor_xor is
    
    signal A :std_logic;
    signal BN :std_logic;
    signal B :std_logic;
    signal NA :std_logic;
    signal o :std_logic;
    
    component iNML_xor_xor is
    port(
    A: in std_logic;
    BN: in std_logic;
    B: in std_logic;
    NA: in std_logic;
    o: out std_logic);
    end component;
    
    begin
    
    DUT : iNML_xor_xor port map(A => A,
    BN => BN,
    B => B,
    NA => NA,
    o => o);
    --------------------------------------------------------------------------------
    -- PLEASE, DO NOT MODIFY BEFORE THIS POINT
    -- USE THIS PROCESS TO INSERT INPUT STIMULI
    -- Please use the following example as a reference:
    -- input_proc: process
    -- begin
    -- in1<='0';
    -- in2<='0';
    -- wait for 30 ns;
    -- in1<='0';
    -- in2<='1';
    -- wait for 30 ns;
    -- in1<='1';
    -- in2<='1';
    -- wait for 30 ns;
    -- in1<='1';
    -- in2<='0';
    -- wait for 100 us;
    -- process input_proc;
    --
    --
    --------------------------------------------------------------------------------
    
    input_proc: process
    begin
     BN <='1';
     NA <='1';
     B <='0';
     A <='0';
     wait for 95 ns;
     BN <='0';
     NA <='1';
     B <='1';
     A <='0';
     wait for 95 ns;
     BN <='1';
     NA <='0';
     B <='0';
     A <='1';
     wait for 95 ns;
     BN <='0';
     NA <='0';
     B <='1';
     A <='1';
    
    wait for 100 ns;
    end process input_proc;
    
    end Behavioural;
    • This reply was modified 3 years, 7 months ago by UmbertoUmberto.
    Attachments:
    #1482
    UmbertoUmberto
    Moderator

    Dear Peyman,

    please attach the “.qll” of your xor gate.

    Umberto

    #1484
    peyman safiripeyman safiri
    Participant

    I atached it.

    Attachments:
    #1494
    FabrizioFabrizio
    Moderator

    Dear Peyman,

    we just released the 1.0.2 version of ToPoliNano fixing the issue.

    • This reply was modified 3 years, 7 months ago by FabrizioFabrizio.
Viewing 11 posts - 1 through 11 (of 11 total)
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