Reducing the Latency

[Chinmay Joshi]

Hello,

I wanted to know if there is a way to reduce the latency in MagCAD. As it is in your full adder circuit, the carry bit comes before the sum bit. Is there a way in which we can reduce the latency of the sum bit and make the carry bit and the sum bit appear simultaneously?

• This topic was modified 6 years, 11 months ago by Fabrizio.

[Fabrizio]

Dear Chinmay,

the total latency related to the number of ANC to be crossed. In principle, to reduce the latency you should reduce the number of gates. Another possibility is to synchronize the two outputs by adding some delays on the fastest path.

Fabrizio

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