magCAD file is closing automatically when i am exporitng the components

[Rishikesh G]

magCAD file is closing automatically when I am exporting the components(rca). The objective is to perform the ripple carry adder I have enclosed the my simulation file and other supporting files for your kind perusal. please me in solving the problem.

• This topic was modified 5 years, 1 month ago by Umberto. Reason: Moved to correct forum: MagCAD HDL Models

Attachments:

1. rca.qll
2. FA_pnml.qll
3. HA_pnml.qll
4. xor_pnml.qll

[Umberto]

Dear Rishikesh,

two files, (and_pnml and or_pNML) are missing and therefore I can’t verify your issue.
Anyway, you posted in the ToPoliNano support but you are using pNML: this technology is not yet supported inside the tool.
Are you referring to MagCAD instead?

[Rishikesh G]

Yes, sir MagCAD(PNML). I am attaching (and_pnml and or_pNML) below sir. Sorry for the trouble…

Attachments:

1. and_pnml.qll
2. or_pnml.qll

[Umberto]

Dear Rishikesh,

the files you provided me have an error in the xor layout. When I tried to export the component I get an error. Is it the same for you? Which version of MagCAD are you using?

[Rishikesh G]

Sir, I am using the latest versions of magCAD.I am getting no errors while simulating xor. Let me re-upload the files so that u can look into the error.

Attachments:

1. and_pnml-1.qll
2. or_pnml-1.qll
3. xor_pnml-1.qll
4. HA_pnml-1.qll

[Rishikesh G]

the follwing files…

Attachments:

1. FA_pnml-1.qll
2. rca-1.qll

[Umberto]

Dear Rishikesh,

I was wrong, there is a problem in the FA file. I get an error during VHDL generation. In fact, the connection with the output of the HA are wrong. Unfortunately, there is a bug somewhere and the tool is not managing properly the error in a file deeper in the hierarchy.
We are working on it. As a workaround, please be sure that all the components in the hierarchy are error free, and generate manually the VHDL for each of them.

This will solve your issue while we work on version 2.8.1.

[Rishikesh G]

In my laptop magCAD is exporting FA file there is no error sir(VHDL generation). And I have checked all the components in the hierarchy they are no errors. Thank you for your responses sir

[Umberto]

Dear Rishikesh,

please be careful because the files you uploaded contains some errors. For example in file xor_pnml the output overlaps the or instance. Please correct and repeat the operation.
In case you updated the files, pleas upload the latest version here.
Thanks

[Rishikesh G]

Sir, I am attaching here the updated files. I have checked it is exporting VHDL code….

Attachments:

1. and_pnml-2.qll
2. or_pnml-2.qll
3. xor_pnml-2.qll
4. HA_pnml-2.qll

[Rishikesh G]

the following full adders and Ripple carry adder circuit

Attachments:

1. FA_pnml-2.qll
2. rca-2.qll

[Umberto]

Dear Rishikesh,

the last version of the files are ok, except rca_pnml. Input a0 is an output pin. Unfortunately, you triggered a bug. We have solved it and the new version of MagCAD will be released soon. Modify the rca layout using an input pin for a0 and everything will be fine.
Update to version 2.9.0 as soon as it will be available and fell free to report any problem.

[Rishikesh G]

Thanks a lot, sir. Now it is working fine…

[Fabrizio]

Dear Rishikesh,

we have just released the new version of the tool with the bug fix and some improvement.

[Author]

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