I am trying to design basic digital circuits using pNML in magCAD. According to the pNML principle, in majority voter if any of its inputs is a fixed 0 or a fixed 1 then it will behave as a NAND gate or NOR gate respectively. But in my circuit layout when i am giving a fixed 0 to one input of the majority voter it is behaving as an AND gate and as a OR gate when a fixed 1 is provided. Here i am giving my circuit layouts. Kindly let me know the fault in my circuit.
This topic was modified 3 years, 10 months ago by Fabrizio. Reason: Simple words a preferable as tags