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#1225
Bandan BhoiBandan Bhoi
Participant

sir,
In pNML minority voter circuit vhdl file is not generating. This is log file generated.

Log of compilation, 01/02/2018 – 17:07:48
Process starts.
14 vhdl items created.
Output match not found for cell -1-2-0

I am requesting you to kindly give the solution.
Thanking you

  • This reply was modified 3 years, 8 months ago by FabrizioFabrizio.
  • This reply was modified 3 years, 8 months ago by FabrizioFabrizio.