Home Forums MagCAD Support HDL Models Error in VHDL Simulation of iNML wire Reply To: Error in VHDL Simulation of iNML wire

#1254
peyman safiripeyman safiri
Participant

my vhdl codes :


--------------------------------------------------------------------------------
-- VHDL description automatically generated by MagCAD                         --
-- Date: 29/01/2018                                                           --
-- Time: 18:55:01                                                             --
--------------------------------------------------------------------------------
-- Entity: iNML/custom/New_1
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NML_definitions.all;
use work.NML_components.all;

entity iNML_custom_New_1 is
port(
	b: out std_logic;
	b_param: out param_data := (others => 0.0);
	A: in std_logic;
	A_param: in param_data := (others => 0.0);
	CLK: in std_logic_vector(0 to 2));
end iNML_custom_New_1;

architecture struct of iNML_custom_New_1 is
for cell3_0: NML_cell use entity work.NML_cell(NML_baseCell);
signal ls3_0o : std_logic;
signal ls3_0o_param : param_data := (others => 0.0);
for cell2_0: NML_cell use entity work.NML_cell(NML_baseCell);
signal ls2_0o : std_logic;
signal ls2_0o_param : param_data := (others => 0.0);
for cell1_0: NML_cell use entity work.NML_cell(NML_baseCell);
signal ls1_0o : std_logic;
signal ls1_0o_param : param_data := (others => 0.0);
for cell0_0: NML_cell use entity work.NML_cell(NML_baseCell);
signal ls0_0o : std_logic;
signal ls0_0o_param : param_data := (others => 0.0);
signal ls4o : std_logic;
signal ls4o_param : param_data := (others => 0.0);
begin
b <= ls3_0o;
b_param <= ls3_0o_param;
cell3_0: NML_cell generic map(NInput => 1,NOutput => 1, inputMode => NORMAL)
	port map(CELL_IN(0) => ls2_0o, PARAM_IN(0) => ls2_0o_param,CELL_OUT(0) => ls3_0o, PARAM_OUT(0) => ls3_0o_param);
cell2_0: NML_cell generic map(NInput => 1,NOutput => 1, inputMode => NORMAL)
	port map(CELL_IN(0) => ls1_0o, PARAM_IN(0) => ls1_0o_param,CELL_OUT(0) => ls2_0o, PARAM_OUT(0) => ls2_0o_param);
cell1_0: NML_cell generic map(NInput => 1,NOutput => 1, inputMode => NORMAL)
	port map(CELL_IN(0) => ls4o, PARAM_IN(0) => ls4o_param,CELL_OUT(0) => ls1_0o, PARAM_OUT(0) => ls1_0o_param);
cell0_0: NML_cell generic map(NInput => 1,NOutput => 1, inputMode => NORMAL)
	port map(CELL_IN(0) => A, PARAM_IN(0) => A_param,CELL_OUT(0) => ls0_0o, PARAM_OUT(0) => ls0_0o_param);
reg4: nml_reg generic map(WireDirection => FORWARD)
	port map(REG_IN => ls0_0o, REG_PARAM_IN => ls0_0o_param,REG_OUT => ls4o, REG_PARAM_OUT => ls4o_param, CLK => CLK(0));
end struct;

and my test bench codes :


--------------------------------------------------------------------------------
-- Testbench automatically generated by MagCAD                         --
-- Date: 29/01/2018                                                           --
-- Time: 18:55:01                                                             --
--------------------------------------------------------------------------------
-- Entity: iNML/custom/New_1
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NML_definitions.all;
use work.NML_components.all;

entity tb_iNML_custom_New_1 is
GENERIC
	(
		phases: natural := 3;
		period: time	:= 10 ns
	);
end tb_iNML_custom_New_1;

architecture Behavioural of tb_iNML_custom_New_1 is

signal base_clk_i : std_logic;
signal clk_i : std_logic_vector (0 to phases-1);
signal b :std_logic;
signal b_param : param_data := (others => 0.0);
signal A :std_logic;
signal A_param : param_data := (others => 0.0);

component iNML_custom_New_1 is
port(
	b: out std_logic;
	b_param: out param_data := (others => 0.0);
	A: in std_logic;
	A_param: in param_data := (others => 0.0);
	CLK: in std_logic_vector(0 to 2));
end component;

begin

DUT : iNML_custom_New_1 port map(b => b, b_param => b_param, 
A => A, A_param => A_param, 
CLK => clk_i);

base_clk_proc: process
begin
	if (base_clk_i = 'U') then
	  base_clk_i <= '0';
	else
	  base_clk_i <= not(base_clk_i);
	end if;
	wait for period/2;
end process base_clk_proc;

out_clk_proc: process(base_clk_i)
begin
    -- Clear undefined states
    for i in 0 to phases-1 loop
    	if (clk_i(i) = 'U') then
            	clk_i <= (others => '0'); -- Reset signal
		clk_i(0) <= '1';
        	exit; -- Force quit

        -- Act as shift register on edge of internal clock
    	elsif (base_clk_i'event AND base_clk_i='1') then
            	if (i = 0) then
                		clk_i(0) <= clk_i(phases-1);
            	else
                		clk_i(i) <= clk_i(i-1);
            	end if;
    	end if;
    end loop;
end process out_clk_proc;
  
input_proc: process
begin
 --insert your input stimuli here 

A <='1'

end process input_proc;

end Behavioural;
  • This reply was modified 3 years, 8 months ago by FabrizioFabrizio.
  • This reply was modified 3 years, 8 months ago by FabrizioFabrizio. Reason: please use the code tag when posting vhdl code and post the whole code in a single reply
  • This reply was modified 3 years, 8 months ago by FabrizioFabrizio.