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I was wrong, there is a problem in the FA file. I get an error during VHDL generation. In fact, the connection with the output of the HA are wrong. Unfortunately, there is a bug somewhere and the tool is not managing properly the error in a file deeper in the hierarchy.
We are working on it. As a workaround, please be sure that all the components in the hierarchy are error free, and generate manually the VHDL for each of them.
This will solve your issue while we work on version 2.8.1.