Home › Forums › MagCAD Support › HDL Models › Error During Simulating using Xilinx ISE › Reply To: Error During Simulating using Xilinx ISE February 27, 2019 at 1:17 pm #1743 FabrizioModerator Hi, you are getting this error because one of the signals is named “sec”, which is a VHDL keyword for seconds. Fabrizio
