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#1716
UmbertoUmberto
Moderator

Hi,
area and latency are not going to change if you use hierarchical approach or not. Those parameters are related to the circuit design, the number of elements, the functionality and the length of the interconnections in pNML technology. The latency in pNML and in general in NML is the time from an applied input to reach the output. Similarly happens in CMOS: if I design a circuit and then place two of them in series the area and delay will increase, no matter what approach (hierarchical/flat) is used. Indeed, if you use “flat insert” for your fulladder you will get the same values as if you insert it as a component. Obviously, your previous designs are different in area and latency since they are different circuits. I report here the definitions and log files for fulladder_box and the same layout where the component has been replaced with flat elements(see pictures).


Fulladder_box                      | Fulladder_box_flat
definitions                        | definitions
-- Entity name: full_adder_box     | -- Entity name: full_adder_box_flat                                         
-- Element list:                   | -- Element list:  
--  Tmagnet         1              | --  Tmagnet         1  
--  -------------------            | --  ---------------------- 
--  via             2              |--  via             2   
--  -------------------            |--  ----------------------  
--  fa1             1              |   
--  -------------------            |--  ----------------------  
--  corner          5              |--  corner          5 
--  -------------------            |--  ----------------------  
--  Xmagnet         1              |--  Xmagnet         1   
--  -------------------            |--  ----------------------  
--  magnet          9              |--  magnet          9   
--  -------------------            |--  ----------------------  
--  mv3             3              |--  mv3             3  
--  -------------------            |--  ----------------------  
--  inverter        20             |--  inverter        20 
--  -------------------            |--  ----------------------  
--  pad             16             | --  pad             16    
--  -------------------            |--  ----------------------  
log                                |log
Bounding box area:  8.1 um^2.      |Bounding box area:  8.1 um^2.

As you can see those circuits are identical.
Let me say that those circuits are also useless: if you designed fulladder1 there is no need to design a circuit that instantiates only a fulladder1 and some interconnections. If you want a 2bit rca you need to add two fulladder1 and connect them properly.

I hope this solves your issue.
Umberto

  • This reply was modified 2 years, 7 months ago by UmbertoUmberto.
  • This reply was modified 2 years, 7 months ago by UmbertoUmberto.