I get that the area will definitely increase. No doubt at that part. But here what I want to say:
The main use of hierarchical method is to reduce circuit complexity without changing its area and latency (Correct me if I am wrong here).
The area will increase because I am adding extra wires, BUT THE LATENCY SHOULD NOT CHANGE WHILE WE USE HIERARCHICAL METHOD while in the above case, the latency also increases while we use the HIERARCHICAL METHOD. I am expecting that the LATENCY SHOULD NOT CHANGE.
Is it that when we will use HIERARCHICAL METHOD the latency and area will increase? If yes, then it is better to design the circuit without HIERARCHICAL METHOD because ultimately we want reduced area and delay.