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February 20, 2019 at 1:22 pm
#1706

Moderator
Hi,
I don’t get the point. Can you please upload the .qll files of the 4.18um2 circuit and the 8.1um2?
In general, the circuit latency depends on the critical path, which is represented by the longest nanowire + nucleation. If a component is inserted in a larger design I would expect that the bounding box area increases.
Fabrizio