Dear Ali,
the HDL parser can accept only structural/post-synthesis VHDL description. This means that for each used gate the corresponding component should be declared within the architecture. ToPoliNano is not a synthesis tool. It takes the nestist and perform the physical design.
In your specific case, the declaration of the XOR gate is missing. However, I would suggest using ONLY the 4 gates supported by the iNML technology as reported in the ToPoliNano documentation, which are:
– AND
– OR
– INV
– MV