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April 4, 2018 at 10:23 am #1420
please do not modify the automatic generated VHDL file. The easiest way to input a fixed ‘0’ in a iNML design is to place an input pin and then use the testbench to force the value. You should give a mnemonic name to that input, such “fixed_0” and then assign the value 0 in the testbench.
The other errors should be simple syntax errors. Please have a look to the VHDL cookbook for help.