Home Forums MagCAD Support HDL Models iNML file(.vhdl) not able to run behavioral code Reply To: iNML file(.vhdl) not able to run behavioral code

#1418
Divyang ThakkarDivyang Thakkar
Participant

Yes, Sir you were right. I have rectified that error and now it is working fine.

In my design of Compressor, I need to input 0 at certain places when I am doing it I am getting error while uploading the necessary files.

The error reads as:


INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" into library work
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 61: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 62: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 65: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 66: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 95: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 96: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 97: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final.vhd" Line 98: Syntax error near "0".
INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" into library work
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 69: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 70: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 73: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 74: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 101: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 102: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 103: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 104: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 460: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 461: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 464: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 465: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 494: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 495: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 496: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 497: Syntax error near "0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 834: Syntax error near "=>".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 836: Syntax error near "=>".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 850: Syntax error near "=>".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/Final_TB.vhd" Line 851: Syntax error near "=>".
INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/Final/library_inml.vhd" into library work
ERROR:ProjectMgmt - 28 error(s) found while parsing design hierarchy.

Sir can you please guide me on how to input 0 in iNML technology.

  • This reply was modified 3 years, 6 months ago by FabrizioFabrizio. Reason: Please use code tags when posting log messages