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March 28, 2018 at 3:36 pm #1411
you are right. library_pnml.vhd is not needed, the files needed for simulation are
Back to your error, it seems you are writing a sort of mixed VHDL/VERILOG 🙂
Please, be careful of writing correct VHDL statement, like the one in the example of “stimuli process” in the automatically generated testbench.
in1<='0'; in2<='0'; wait for 30 ns;