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#1405
Divyang ThakkarDivyang Thakkar
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I am creating a Half Adder which has 2 inputs: X0 and X1.
After Exporting the HalfAdder.qll file I am not getting the library_pnml.vhd file in the VHDL folder; Althought he export was successful and the vhdl file was generated.

On Including the files:
– <circuit_name>.vhd
– library_inml.vhd
– <circuit_name>_TB.vhd
And giving the test bench input for HalfAdder file I am getting the following error:

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/HalfAdder/HalfAdder_TB.vhd" into library work
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/HalfAdder/HalfAdder_TB.vhd" Line 88: Syntax error near "X0".
ERROR:HDLCompiler:806 - "C:/Users/Divyang Thakkar/MagCADFiles/VHDL/HalfAdder/HalfAdder_TB.vhd" Line 89: Syntax error near "'".
ERROR:ProjectMgmt - 2 error(s) found while parsing design hierarchy.

The Input Test Bench is as follows:

--insert your input stimuli here 

wait for 10us;

assign X0<=1'b0;
assign X1<=1'b1;
  • This reply was modified 3 years, 6 months ago by FabrizioFabrizio. Reason: Please use code tags to add vhdl code or log messages
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