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January 31, 2018 at 8:18 am
#1209
![Umberto](https://topolinano.polito.it/wp-content/uploads/ultimatemember/15/profile_photo-80x80.jpg?1722076419)
Moderator
Hi,
did you check the log file in the VHDL folder?
It would be better if you show your design without the error message.
Umberto