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Reply To: Error in VHDL Simulation of iNML wire

Home › Forums › MagCAD Support › HDL Models › Error in VHDL Simulation of iNML wire › Reply To: Error in VHDL Simulation of iNML wire

February 8, 2018 at 4:47 pm #1259
UmbertoUmberto
Moderator

Hi,
you missed a “;” in your assignment.
Furthermore a wait statement is needed inside the stimuli process.
For example:

A <='1';
wait for 10 ns;
A <='0';
wait for 10 us;
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