Simulation for half adder

Tagged: half adder, pNML, simulation

This topic has 5 replies, 2 voices, and was last updated 6 years, 10 months ago by Chinmay Joshi.

Viewing 6 posts - 1 through 6 (of 6 total)

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January 1, 2018 at 10:15 am #1139
Chinmay Joshi
Participant
Hi Fabrizio,

I am trying to implement half adder circuit. The problem is that i’m getting the correct outputs for all inputs except when all inputs are 1. Here is the circuit in MagCAD and the output waveform.
- This topic was modified 6 years, 10 months ago by Fabrizio.
- This topic was modified 6 years, 10 months ago by Fabrizio.
Attachments:
1. half-adder.jpg
2. half-adder-waveform.jpg
January 2, 2018 at 4:12 pm #1142

Fabrizio
Moderator

Hi Chinmay,

I think there is an error in the Sum function you are implementing. Try to design it by using only minority in NAND configuration.

Fabrizio

January 2, 2018 at 5:44 pm #1147
Chinmay Joshi
Participant
Hi Fabrizio,

Here is my circuit for half adder using minority NAND configuration. I am still getting the wrong output.
Attachments:
1. half-adder1.jpg
2. half-adder-waveform1.jpg
January 2, 2018 at 5:51 pm #1150

Chinmay Joshi
Participant

With the above design, all the outputs are coming wrong except when all inputs are 0

January 2, 2018 at 9:20 pm #1151
Fabrizio
Moderator
Dear Chinmay,

you get a wrong behavior because two gates are not implementing the NAND function (see attachment). When you use 3D gates you should pay attention at the coupling between input magnets and ANC. Magnets lying on the same physical plane are coupled anti-ferromagnetically with ANC. On the contrary, inputs placed above or below the ANC are coupled ferromagnetically.

Please have a look at the following papers:

paper 1
paper 2
Attachments:
1. half_hadder_errors.jpg
January 3, 2018 at 6:24 pm #1156

Chinmay Joshi
Participant

Hi Fabrizio,

Thanks for the help. I got the output now.
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