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  • December 19, 2017 at 7:08 pm #1092
    Sagar AgrawalSagar Agrawal
    Participant

    Hi
    I just started using the MagCAD tool last week and have worked through the basics of pNML design. By referring to the research paper, ‘MagCAD: Tool for the Design of 3-D Magnetic Circuits’ and the MagCAD User guide I have learnt how to create basic 2 input logic gates such as ‘And’ and ‘Or’. I have attached the schematic of a 2 input ‘and’ and ‘or’ gate I created.

    OR
    AND

    Using these basic gates I can also design a full adder circuit. While reading through the research paper, however, I came across a full adder circuit which uses only 3 , 3 input gates. I implemented it and verified the result. The circuit schematic is attached here. I would like to know the procedure by which we can minimise the gates while implementing a boolean expression.

    Full-Adder

    Thank You
    Sagar Agrawal

    December 20, 2017 at 9:43 am #1098
    FabrizioFabrizio
    Moderator

    Hi,
    from you screenshots I see two identical gates implementing a 2 input NAND gate. The nucleation center surrounded by 3 inputs implements a negated majority voter.
    To optimize circuits, I suggest you to synthetize the boolean network with ABC or by using MIG before drawing the schematics with MagCAD.

    • This reply was modified 6 years, 11 months ago by FabrizioFabrizio.
    December 20, 2017 at 1:31 pm #1100
    Sagar AgrawalSagar Agrawal
    Participant

    Thanks a lot for the suggestion. I will look into majority inverter graph and I’ll try to optmise my circuit. 🙂

    The two gates I attached earlier work as ‘AND’ and ‘OR’ when I simulated them. I have attached the timing diagrams below

    AND timing diagram
    OR timing diagram

    • This reply was modified 6 years, 11 months ago by FabrizioFabrizio.
    December 20, 2017 at 2:12 pm #1102
    FabrizioFabrizio
    Moderator

    You are right. I was considering the value on the magnets, which is inverted.

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