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December 20, 2017 at 9:43 am
#1098
![Fabrizio](https://topolinano.polito.it/wp-content/uploads/ultimatemember/28/profile_photo-80x80.jpg?1722079013)
Moderator
Hi,
from you screenshots I see two identical gates implementing a 2 input NAND gate. The nucleation center surrounded by 3 inputs implements a negated majority voter.
To optimize circuits, I suggest you to synthetize the boolean network with ABC or by using MIG before drawing the schematics with MagCAD.
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This reply was modified 6 years, 7 months ago by
Fabrizio.