Reply To: Optimising the design to implement Boolean expressions

[Fabrizio]

Hi,
from you screenshots I see two identical gates implementing a 2 input NAND gate. The nucleation center surrounded by 3 inputs implements a negated majority voter.
To optimize circuits, I suggest you to synthetize the boolean network with ABC or by using MIG before drawing the schematics with MagCAD.

• This reply was modified 7 years, 11 months ago by Fabrizio.