- This topic has 3 replies, 2 voices, and was last updated 7 years, 11 months ago by
.
-
Posts
-
Hi
I just started using the MagCAD tool last week and have worked through the basics of pNML design. By referring to the research paper, ‘MagCAD: Tool for the Design of 3-D Magnetic Circuits’ and the MagCAD User guide I have learnt how to create basic 2 input logic gates such as ‘And’ and ‘Or’. I have attached the schematic of a 2 input ‘and’ and ‘or’ gate I created.Using these basic gates I can also design a full adder circuit. While reading through the research paper, however, I came across a full adder circuit which uses only 3 , 3 input gates. I implemented it and verified the result. The circuit schematic is attached here. I would like to know the procedure by which we can minimise the gates while implementing a boolean expression.
Thank You
Sagar AgrawalHi,
from you screenshots I see two identical gates implementing a 2 input NAND gate. The nucleation center surrounded by 3 inputs implements a negated majority voter.
To optimize circuits, I suggest you to synthetize the boolean network with ABC or by using MIG before drawing the schematics with MagCAD.Thanks a lot for the suggestion. I will look into majority inverter graph and I’ll try to optmise my circuit. 🙂
The two gates I attached earlier work as ‘AND’ and ‘OR’ when I simulated them. I have attached the timing diagrams below
- The topic ‘Optimising the design to implement Boolean expressions’ is closed to new replies.